Silicon Ocean Ultra Low Power AAC Decoder ASIC Core (AAC-SO1)

The AAC-SO1 decoder ASIC core is designed for low power AAC decoding applications.  The AAC-SO1 can be seamlessly integrated with Silicon Ocean MP3 decoder WMAMP3-SO3 for a new generation of low power, low cost MP3/WMA/AAC decoding chips.

1.   Important Features

·     All AAC decoding functions implemented at RTL level

·     Gate count 75 K gates plus 32K bytes data RAM

·     Lowest power consumption (clock required 10 MHz)

·     Single clock synchronous design

·     Support AAC Low complexity, Main profile and VBR variant Apple iTune audio decoding

·     Straightforward interfaces for SoC applications

·     Fully synthesizable technology independent of verilog RTL code

2. Function Overview

AAC-SO1 takes any AAC bitstream, automatically detects the header and extracts all header/side information, and then uses the information to decode compressed AAC bit stream. The output from the AAC-SO1 is 16 bits PCM samples. These PCM samples can be transferred to audio DAC via I2S bus or through a rate converter to a low cost fixed sample rate audio DAC.

3. AAC-SO1 top level interface

Deliverables

·      Synthesizable verilog source code

·      Verilog testbench

Please email info@SiliconOcean.com for more information